1. FIELD OF THE INVENTION
The present invention relates to a portable type semiconductor data storage apparatus and a method of protecting data stored in that data storage apparatus. Particularly, the present invention pertains to means for preventing erroneous writing in and reading out of data which may occur while data in the portable type semiconductor data storage apparatus is being accessed and the apparatus is removed from or inserted into a terminal machine.
2. DESCRIPTION OF THE RELATED ART
FIG. 6 shows the circuit configuration of a conventional portable type semiconductor storage apparatus. A cell 6 is connected to a volatile memory 1 through an internal power line 11 for supplying power from a power source, a reverse charge preventing diode 4 and a current limiting resistor 5. A power input line 10 is connected to the internal power line 11 through a reverse-flow preventing diode 2. An address bus 12, a data bus 13, an output enable signal line 14 and a write enable signal line 15 are also connected to the volatile memory 1. A chip enable signal line 16 is also connected to the volatile memory 1 through a three-state non-inverter 19a. A power control circuit 3 is connected between the power input line 10 and the three-state non-inverter 19a. In FIG. 6, reference numerals 7a and 8 denote pull-down resistors, and a reference numeral 9 denotes a pull-up resistor.
When used, the storage apparatus of the aforementioned configuration is mounted on a terminal machine (not shown). Once the storage apparatus is mounted on a terminal machine, power is supplied through the power input line 10 and the diode 2 to the internal power line 11. When the voltage on the power input line 10 is not higher than a predetermined value, the protect signal output from the power control circuit 3 to the three-state non-inverter 19a is at "L" level. Consequently, the non-inverter 19a is in a disabled state, and the terminal machine thus cannot gain access to the memory 1. Thereafter, the voltage on the power input line 10 gradually rises and reaches the predetermined value. At that time, the protect signal output from the power control circuit 3 rises to the "H" level, and the non-inverter 19a is thereby enabled. The memory 1 becomes accessible by the terminal machine.
When no power is supplied to the power input line 10 from the terminal machine because of completion of access or because of non-operation of the storage apparatus, the protect signal from the power control circuit 3 is at "L" level. Consequently, the non-inverter 19a is in a disabled state, and access to the memory 1 is inhibited. At that time, no power is supplied to the memory 1 from the power input line 10. However, power is supplied from the cell 6 to the memory 1 through the resistor 5 and diode 4, and the data stored in the memory 1 is not thus destroyed on the removal of the storage apparatus from the terminal machine.
However, when the storage apparatus is removed from the terminal machine while the terminal machine is accessing the memory 1, a chattering waveform is generated over a very long period of time as compared with the access time on the address bus 12, data bus 13, output enable signal line 14, write enable signal line 15 and chip enable signal line 16 connected to the memory 1. The period during which chattering is generated is in general about several tens of ms, whereas the access time to the memory 1 is 250 ns at the longest. Therefore, the memory 1 cannot be timed correctly, and erroneous writing in or reading out of data may occur. In other words, the accuracy of the data accessed during the chattering cannot be guaranteed.